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USB4640/USB4640i High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller
PRODUCT FEATURES
General Description The SMSC USB4640/USB4640i is a Hi-Speed HSIC USB hub and card reader combo solution with an upstream port compliant to HSIC 1.0, a supplement to the USB 2.0 specification. The two downstream ports are compliant with the USB 2.0 specification. High Speed Inter-Chip (HSIC) is a digital interconnect bus that enables the use of USB technology as a low-power chip-to-chip interconnect at speeds up to 480 Mb/s. The HSIC interface is an industry standard 2-pin digital interface which uses standard USB software. The SMSC USB4640/USB4640i provides an ultra fast interface between an HSIC enabled host and today's popular flash media formats. The controller allows read/write capability to flash media from the following families: - - - - Secure DigitalTM (SD) MultiMediaCardTM (MMC) Memory Stick(R) (MS) xD Picture CardTM (xD)1 Features Compliance with the following flash media card specifications SD 2.0 / MMC 4.2 / MS 1.43 / MS-Pro 1.02 / MS-Pro-HG 1.01 / MS-Duo 1.10 / xD 1.2 Low-power digital HSIC interface offers a replacement for onboard host and device connection for analog USB bus cable HSIC interface enables printers, mobile PCs, ultra-mobile PCs, and cell phone products to reduce the total power budget while taking full advantage of USB connectivity and compatibility with existing USB drivers and software External 1.2 V reference allows upstream and downstream HSIC links to use the same voltage reference Supports a single external 3.3 V supply source; internal regulators provide 1.8 V internal core voltage for additional bill of materials and power savings The transaction translator (TT) in the hub supports operation of Full-Speed and Low-Speed peripherals 9 K RAM | 64 K on-chip ROM Enhanced EMI rejection and ESD protection performance Hub and flash media reader/writer configuration from a single source: External I2C(R) ROM or external SPI ROM
-- Configures internal code using an external I2C EEPROM -- Supports external code using an SPI Flash EEPROM -- Customizable vendor ID, product ID, and language ID if using an external EEPROM
Datasheet
The USB4640/USB4640i offers a versatile, cost-effective, and energy-efficient hub controller with 2 downstream USB 2.0 ports. This combo solution leverages SMSC's innovative technology that delivers industry-leading data throughput in mixed-speed USB environments. Average sustained transfer rates exceeding 35 MB/s are possible2. Highlights Upstream HSIC port and 2 exposed Hi-Speed USB 2.0 downstream ports for external peripheral expansion The dedicated flash media reader is internally attached to a 3rd downstream port of the hub as a USB Compound Device
-- a single or multiplexed flash media reader interface
PortMap
-- Flexible port mapping and port disable sequencing supports multiple platform designs
Up to 9 configurable GPIOs for special functions The USB4640 supports the commercial temperature range of 0C to +70C The USB4640i supports the industrial temperature range of -40C to +85C 48-pin QFN lead-free, RoHS compliant package (7x7 mm) Applications 3G/4G handsets, smartphones, cell phones, and other mobile devices Desktop and mobile PCs Printers GPS navigation systems Media players/viewers Consumer A/V Set-top boxes Industrial products
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PortSwap
-- Programmable USB differential-pair pin locations eases PCB design by aligning USB signal traces directly to connectors
PHYBoost
-- Programmable USB transceiver drive strength recovers signal integrity
1.For xD-Picture CardTM support, please obtain a user license from the xD-Picture Card License Office. 2.Host and media dependent. SMSC USB4640/USB4640i
DATASHEET
High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
ORDER NUMBERS: USB4640/USB4640i-HZH for 48-PIN, QFN LEAD-FREE RoHS COMPLIANT PACKAGE
Please contact your local SMSC representative for more information.
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC makes the following part-numbered device available for purchase only by customers who are xD-Picture Card licensees: USB4640/USB4640i. By purchasing or ordering any of such devices, Buyer represents, warrants, and agrees that Buyer is a duly licensed Licensee under an xD-Picture CardTM License Agreement with Fuji Photo Film Co., Ltd., Olympus Optical Co., Ltd., and Toshiba Corporation; and that Buyer will maintain in effect such xD-Picture Card license and will give SMSC reasonable advance notice of any termination or expiration of such xD-Picture Card license, but in no event less than five days advance notice. SMSC may discontinue making such devices available for purchase by Buyer and/or discontinue further deliveries of such devices if such xD-Picture Card license shall expire, terminate, or cease to be in force, or if Buyer is or becomes in default of such xD-Picture Card license. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
Table of Contents
Chapter 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chapter 3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chapter 5 Pin Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 48-Pin Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 6.2 6.3 6.4 USB4640/USB4640i Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM BOOT Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 21 22 24
Chapter 7 Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 8 Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 8.2 8.3 8.4 Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 Hub Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Card Reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 EEPROM/SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 EEPROM Data Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set bit 7 of bmAttribute to enable the registers in Table 8.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 EEPROM Data Descriptor Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 A0h-A7h: Device Power Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3 Device ID Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4 Hub Controller Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.5 Internal Flash Media Controller Extended Configurations . . . . . . . . . . . . . . . . . . . . . . . . 8.4.6 I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.7 In-Circuit EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Configuration Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.1 Internal POR Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.2 External Hardware nRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.3 USB Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 28 28 28 28 29 32 32 37 39 40 50 50 51 51 51 51 51 52
8.5 8.6
Chapter 9 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.1 9.2 9.3 Oscillator/Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic Resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.2 USB 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 54 54 54 54
Chapter 10 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.1 10.2 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
10.3 10.4
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Chapter 11 GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Chapter 12 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.1 Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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List of Tables
Table 5.1 USB4640/USB4640i 48-Pin Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.1 USB4640/USB4640i Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.2 USB4640/USB4640i Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.1 Legend for Pin Reset States Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.2 USB4640/USB4640i Reset States Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.1 Internal Flash Media Controller Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.2 Hub Controller Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.3 Other Internal Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.4 Internal Flash Media Controller Extended Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.5 Port Map Register for Ports 1 & 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.6 Port Map Register for Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.7 nRESET Timing for EEPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 9.1 Crystal Circuit Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 10.1 Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 11.1 USB4640/USB4640i GPIO Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 15 21 25 25 29 31 31 32 48 49 52 53 60 61
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List of Figures
Figure 3.1 Figure 4.1 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 7.1 Figure 8.1 Figure 9.1 Figure 9.2 Figure 9.3 Figure 10.1 Figure 12.1 Figure 12.2 Figure 12.3 USB4640/USB4640i 48-Pin QFN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB4640/USB4640i Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Power Control with USB Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Power Control with a Single Poly Fuse and Multiple Loads . . . . . . . . . . . . . . . . . . . . . . Port Power with Ganged Control with Poly Fuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI ROM Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nRESET Timing for EEPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance Formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic Resonator Usage with SMSC IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Rise Time Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB4640/USB4640i 48-Pin QFN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-Pin Package Tape Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-Pin Package Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 22 23 23 24 24 25 52 53 53 54 55 62 63 64
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Chapter 1 Overview
The SMSC USB4640/USB4640i is a Hi-Speed HSIC USB hub and card reader combo solution with an upstream port compliant to HSIC 1.0, a supplement to the USB 2.0 specification. The two downstream ports are compliant with the USB 2.0 specification. In addition, The dedicated flash media reader/writer is internally attached to a 3rd downstream port of the hub as a USB Compound device. High Speed Inter-Chip (HSIC) is a digital interconnect bus that enables the use of USB technology as a low-power chip-to-chip interconnect at speeds up to 480 Mb/s. Please refer to the "High-Speed Inter-Chip USB Electrical Specification Revision 1.0 as of September 23, 2007" which can be found at http://www.usb.org/developers/docs/docs. This combo solution supports today's popular multiformat flash media cards. This multi-format flash media controller and USB hub combo features two exposed downstream USB ports available for external peripheral expansion. The USB4640/USB4640i will attach to an upstream port as a Full-Speed hub or as a Full-/Hi-Speed hub. The hub supports Low-Speed, Full-Speed, and Hi-Speed (if operating as a Hi-Speed hub) downstream devices on all of the enabled downstream ports. All required resistors on the USB ports are integrated into the hub. This includes all series termination resistors on D+ and D- pins and all required pull-down and pull-up resistors. The overcurrent sense inputs for the downstream facing ports have internal pull-up resistors. The USB4640/USB4640i includes programmable features such as: PortMap which provides flexible port mapping and disable sequences. The downstream ports of a USB4640/USB4640i hub can be reordered or disabled in any sequence to support multiple platform designs with minimum effort. For any port that is disabled, the USB4640/USB4640i automatically reorders the remaining ports to match the USB host controller's port numbering scheme. PortSwap which adds per-port programmability to USB differentialpair pin locations. PortSwap allows direct alignment of USB signals (D+/D-) to connectors avoiding uneven trace length or crossing of the USB differential signals on the PCB. PHYBoost which enables four programmable levels of USB signal drive strengths in downstream port transceivers. PHYBoost attempts to restore USB signal integrity. The diagram on the right shows an example of Hi-Speed USB eye diagrams before (PHYBoost at 0%) and after (PHYBoost at 12%) signal integrity restoration in a compromised system environment.
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Hardware Features
Single chip HSIC hub and flash media controller combo USB4640 supports the commercial temperature range of 0C to +70C USB4640i supports the industrial temperature range of -40C to +85C Transaction translator (TT) in the hub supports operation of FS and LS peripherals Full power management with individual or ganged power control of each downstream port Optional support for external firmware access via SPI interface Onboard 24 MHz crystal driver circuit Optional external 24 MHz clock input which must be a 1.8 V signal Code execution via SPI ROM which must meet - 30 MHz or 60 MHz operation support - Single bit or dual bit mode support - Mode 0 or mode 3 SPI support Compliance with the following flash media card specifications: Secure Digital 2.0 / MultiMediaCard 4.2 - SD 2.0, SD-HS, SD-HC - TransFlashTM and reduced form factor media - 1/4/8 bit MMC 4.2 Memory Stick 1.43 Memory Stick Pro Format 1.02 Memory Stick Pro-HG Duo Format 1.01 - Memory Stick, MS Duo, MS-HS, MS Pro-HG, MS Pro Memory Stick Duo 1.10 xD-Picture Card 1.2 Up to 9 GPIOs: Configuration and polarity for special function use - The number of actual GPIOs depends on the implementation configuration used - One GPIO available with up to 200 mA drive and protected "fold-back" short circuit current 8051 8-bit microprocessor - 60 MHz - single cycle execution - 64 KB ROM | 9 KB RAM Integrated regulator for 1.8 V core operation
Software Features
Hub and flash media reader/writer configuration from a single source: External I2C ROM or external SPI ROM If the OEM is using an external EEPROM or an external SPI ROM, the following features are available: - Customizable vendor ID, product ID, and device ID - 12-hex digits maximum for the serial number string - 28-character manufacturer ID and product strings for the flash media reader/writer
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OEM Selectable Hub Features
A default configuration is available in the USB4640/USB4640i following a reset. The USB4640/USB4640i may also be configured by an external I2C EEPROM or via external SPI ROM flash. Compound Device support on a port-by-port basis - a port is permanently hardwired to a downstream USB peripheral device Select over-current sensing and port power control on an individual or ganged (all ports together) basis to match the OEM's choice of circuit board component selection Port power control and over-current detection/delay features Configure the delay time for filtering the over-current sense inputs Configure the delay time for turning on downstream port power Bus- or self-powered selection Hub port disable or non-removable configurations Flexible port mapping and disable sequencing supports multiple platform designs Programmable USB differential-pair pin location eases PCB layout by aligning USB signal lines directly to connectors Programmable USB signal drive strength recovers USB signal integrity using 4 levels of signal drive strength Indicate the maximum current that the 2-port hub consumes Indicate the maximum current required for the hub controller
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High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
Chapter 2 Acronyms
ACK: Handshake packet (positive acknowledgement) EOF: End of (micro) Frame FM: Flash Media FMC: Flash Media Controller FS: Full-Speed Device LS: Low-Speed Device HS: Hi-Speed Device I2C(R): Inter-Integrated Circuit1 MMC: MultiMediaCard MS: Memory Stick MSC: Memory Stick Controller OCS: Over-current Sense PHY: Physical Layer PLL: Phase-Locked Loop RXD: Received eXchange Data SD: Secure Digital SDC: Secure Digital Controller TXD: Transmit eXchange Data UART: Universal Asynchronous Receiver-Transmitter UCHAR: Unsigned Character UINT: Unsigned Integer
Standard Microsystems is a registered trademark and SMSC is a trademark of Standard Microsystems Corporation. Other product and company names are trademarks or registered trademarks of their respective holders. *Note: In order to develop, make, use, or sell readers and/or other products using or incorporating any of the SMSC devices made the subject of this document or to use related SMSC software programs, technical information and licenses under patent and other intellectual property rights from or through various persons or entities, including without limitation media standard companies, forums, and associations, and other patent holders may be required. These media standard companies, forums, and associations include without limitation the following: Sony Corporation (Memory Stick, Memory Stick Pro); SD3 LLC (Secure Digital); MultiMedia Card Association (MultiMediaCard); the SSFDC Forum (SmartMedia); the Compact Flash Association (Compact Flash); and Fuji Photo Film Co., Ltd., Olympus Optical Co., Ltd., and Toshiba Corporation (xD-Picture Card). SMSC does not make such licenses or technical information available; does not promise or represent that any such licenses or technical information will actually be obtainable from or through the various persons or entities (including the media standard companies, forums, and associations), or with respect to the terms under which they may be made available; and is not responsible for the accuracy or sufficiency of, or otherwise with respect to, any such technical information. SMSC's obligations (if any) under the Terms of Sale Agreement, or any other agreement with any customer, or otherwise, with respect to infringement, including without limitation any obligations to defend or settle claims, to reimburse for costs, or to pay damages, shall not apply to any of the devices made the subject of this document or any software programs related to any of such devices, or to any combinations involving any of them, with respect to infringement or claimed infringement of any existing or future patents related to solid state disk or other flash memory technology or applications ("Solid State Disk Patents"). By making any purchase of any of the devices made the subject of this document, the customer represents, warrants, and agrees that it has obtained all necessary licenses under then-existing Solid State Disk Patents for the manufacture, use and sale of solid state disk and other flash memory products and that the customer will timely obtain at no cost or expense to SMSC all necessary licenses under Solid State Disk Patents; that the manufacture and testing by or for SMSC of the units of any of the devices made the subject of this document which may be sold to the customer, and any sale by SMSC of such units to the customer, are valid exercises of the customer's rights and licenses under such Solid State Disk Patents; that SMSC shall have no obligation for royalties or otherwise under any Solid State Disk Patents by reason of any such manufacture, use, or sale of such units; and that SMSC shall have no obligation for any costs or expenses related to the customer's obtaining or having obtained rights or licenses under any Solid State Disk Patents. SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR OTHER VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES AGAINST INFRINGEMENT AND THE LIKE. No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark, copyright, mask work right, trade secret, or other intellectual property right. **To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect. Forms of these Software License Agreements may be obtained by contacting SMSC.
1.I2C is a registered trademark of Philips Corporation.
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High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
Chapter 3 Pin Configuration
SD_D3 / MS_D3 / xD_D6
SD_D4 / MS_D2 / xD_D7
GPIO10 (CRD_PWR)
GPIO14 / xD_nCD
GPIO12 / MS_INS
SD_D2 / xD_D5
GPIO2 / RXD
xD_nB/R
xD_nRE
xD_nCE
VDD33
36
35
34
33
32
31
30
29
28
27
26
GPIO1 / LED / TXD nRESET HSIC_IMP TEST VDD12 HSIC_DAT HSIC_STROBE XTAL2 XTAL1 (CLKIN) PLLFILT RBIAS VDD33
37 38 39 40 41 42 43 44 45 46 47 48 10 11 12 1 2 3 4 5 6 7 8 9 Ground Pad (must be connected to VSS)
25 24 23 22 21 20 19 18 17 16 15 14 13
VDD33
SD_CMD / MS_D0 / xD_CLE SD_D5 / MS_D1 / xD_ALE xD_nWE SD_CLK / MS_BS / xD_nWP SD_D6 / MS_D7 / xD_D0 SD_D7 / MS_D6 / xD_D1 SD_D0 / MS_D4 / xD_D2 SD_D1 / MS_D5 / xD_D3 VDD33 CRFILT GPIO15 / SD_nCD GPIO6 / SD_WP / MS_SCLK / xD_D4
SMSC USB4640/40i (Top View QFN-48)
USBDN_DP2
USBDN_DP3
USBDN_DM2
USBDN_DM3
SPI_CE_n
SPI_DO / GPIO5 / SDA / SPI_SPD_SEL
SPI_CLK / GPIO4 / SCL
VDD33
PRTCTL2
PRTCTL3
Indicates pins on the bottom of the device.
Figure 3.1 USB4640/USB4640i 48-Pin QFN
SMSC USB4640/USB4640i
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VDD33
SPI_DI
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1.2 V 1.8 V 24 MHz Crystal 3.3 V
HSIC Data & Strobe
Chapter 4 Block Diagram
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1.8 V Reg PLL SFR RAM Controller RAM 6K ROM 64 K GPIOs GPIO Program Memory I/O Bus Transaction Translator Port Controller ADDR MAP PWR_FET0 SPI 8051 PROCESSOR Serial Interface Serial Interface Engine
SPI (4 pins) GPIO10 (CRD_PWR) 8 pins
HSIC
HSIC Impedance
Repeater
3.3 V
1.8 V Reg XDATA BRIDGE + BUS ARBITER EP0 TX EP0 RX 3K total RAM EP2 RX EP2 RX EP2 TX BUS INTFC
VDDCR
Figure 4.1 USB4640/USB4640i Block Diagram
DATASHEET
PHY
Port #2 OC Sense Switch Driver
High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller
12
BRIDGE SIE CTL BUS INTFC *For xD-Picture CardTM support, please obtain a user license from the xD-Picture Card License office.
USB Data OC Sense/ Downstream Pwr Switch
Routing & Port Re-Ordering Logic
AUTO_CBW PROC
BUS INTFC
FMDU CTL
PHY
Port #3 OC Sense Switch Driver
FMI
xD*
MS
SD/ MMC/ SDIO
SMSC USB4640/USB4640i
USB Data Downstream
OC Sense/ Pwr Switch
Datasheet
Flash Media Cards (require Combo socket)
High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
Chapter 5 Pin Table
5.1 48-Pin Table
Table 5.1 USB4640/USB4640i 48-Pin Table UPSTREAM HSIC INTERFACE (3 PINS)
HSIC_IMP
HSIC_DAT
HSIC_STROBE
DOWNSTREAM USB INTERFACE (3 PINS)
XTAL1 (CLKIN)
XTAL2
RBIAS
DOWNSTREAM 2-PORT USB INTERFACE (6 PINS)
USBDN_DP2
USBDN_DM2
PRTCTL2
PRTCTL3
USBDN_DP3
USBDN_DM3
SECURE DIGITAL / MEMORY STICK / xD INTERFACE (18 PINS) SD_D7 / MS_D6 / xD_D1 SD_D3 / MS_D3 / xD_D6 SD_CLK / MS_BS / xD_nWP GPIO6 / SD_WP / MS_SCLK / xD_D4 xD_nRE SD_D6 / MS_D7 / xD_D0 SD_D2 / xD_D5 SD_CMD / MS_D0 / xD_CLE GPIO14 / xD_nCD SD_D5 / MS_D1 / xD_ALE SD_D1 / MS_D5 / xD_D3 GPIO15 / SD_nCD SD_D4 / MS_D2 / xD_D7 SD_D0 / MS_D4 / xD_D2 GPIO12 / MS_INS
xD_nWE
xD_nB/R
xD_nCE SPI INTERFACE (4 PINS) SPI_CLK / GPIO4 / SCL SPI_DO / GPIO5 / SDA / SPI_SPD_SEL
13
SPI_CE_n
SPI_DI
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Table 5.1 USB4640/USB4640i 48-Pin Table MISC (5 PINS) nRESET TEST GPIO1 / LED / TXD GPIO2 / RXD
GPIO10 (CRD_PWR) POWER (9 PINS) (6) VDD33 VDD12 TOTAL 48 CRFILT PLLFILT
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Chapter 6 Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The pin descriptions below are applied when using the internal default firmware and can be referenced in Chapter 8, "Configuration Options," on page 28. Please reference Chapter 2, "Acronyms," on page 10 for a list of the acronyms used. The "n" symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. When "n" is not present in the signal name, the signal is asserted at a high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of "active low" and "active high" signals. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.
6.1
USB4640/USB4640i Pin Descriptions
Table 6.1 USB4640/USB4640i Pin Descriptions 48-PIN QFN BUFFER TYPE (Table 6.2)
SYMBOL
DESCRIPTION
UPSTREAM HSIC INTERFACE HSIC_IMP 39 I HSIC Impedance Control This pin selects the driver impedance of the HSIC_DAT and HSIC_STROBE pins. `1' = approximately 50 impedance `0' = approximately 40 impedance HSIC_DAT 42 I/O HSIC Data This is the bi-directional double data rate (DDR) data signal that is synchronous to the HSIC_STROBE signal as defined in the HighSpeed Inter-Chip USB Specification, Version 1.0. HSIC_STROBE 43 I/O HSIC Strobe This pin is the bi-directional data strobe signal that is defined in the High-Speed Inter-Chip USB Specification, Version 1.0. DOWNSTREAM USB INTERFACE USBDN_DM [3:2] USBDN_DP [3:2] 3 1 4 2 I/O-U USB Bus Data These pins connect to the downstream USB bus data signals and can be swapped using the PortSwap feature (See Section 8.4.4.20, "F1h: Port Swap," on page 47).
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Table 6.1 USB4640/USB4640i Pin Descriptions (continued) 48-PIN QFN 7 6 BUFFER TYPE (Table 6.2) I/OD6PU
SYMBOL PRTCTL[3:2]
DESCRIPTION USB Power Enable As an output, these pins enable power to downstream USB peripheral devices and have weak internal pull-up resistors. See Section 6.3, "Port Power Control" for diagram and usage instructions. As an input, when the power is enabled, these pins monitor the overcurrent condition. When an over-current condition is detected, the pins turn the power off.
RBIAS
47
I-R
USB Transceiver Bias A 12.0 k, 1.0% resistor is attached from VSS to this pin in order to set the transceiver's internal bias currents.
XTAL1 (CLKIN)
45
ICLKx
24 MHz Crystal Input or External Clock Input This pin can be connected to one terminal of the crystal or it can be connected to an external 24 MHz clock when a crystal is not used.
XTAL2
44
OCLKx
24 MHz Crystal Output This is the other terminal of the crystal or it is left open when an external clock source is used to drive XTAL1(CLKIN). SECURE DIGITAL INTERFACE
SD_D[7:0]
19 20 23 30 32 33 17 18 21
I/O8PU
Secure Digital Data 7-0 These are the bi-directional data signals SD_D0 - SD_D7 with weak pull-up resistors.
SD_CLK
O8
Secure Digital Clock This is an output clock signal to the SD/MMC device.
SD_CMD
24
I/O8PU
Secure Digital Command This is a bi-directional signal that connects to the CMD signal of the SD/MMC device. The bi-directional signal has a weak internal pullup resistor.
GPIO15 /
14
I/O6
This general purpose pin may be used either as input, edge sensitive interrupt input, or output. Custom firmware is required to activate this function. Secure Digital Card Detect GPIO This is a GPIO designated by the default firmware as the Secure Digital card detection pin and has an internal pull-up.
SD_nCD
I/O8PU
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High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
Table 6.1 USB4640/USB4640i Pin Descriptions (continued) 48-PIN QFN 13 BUFFER TYPE (Table 6.2) I/O6
SYMBOL GPIO6 /
DESCRIPTION This general purpose pin may be used either as input, edge sensitive interrupt input, or output. Custom firmware is required to activate this function. Secure Digital Write Protected GPIO This is a GPIO designated by the default firmware as the Secure Digital card interface mechanical write protect detect pin. MEMORY STICK INTERFACE
SD_WP
I/O8
MS_BS
21
O8
Memory Stick Bus State This pin is connected to the bus state pin of the MS device. It is used to control the Bus States 0, 1, 2, and 3 (BS0, BS1, and BS3) of the MS device.
GPIO12 /
31
I/O8
This general purpose pin may be used either as input, edge sensitive interrupt input, or output. Custom firmware is required to activate this function. Memory Stick Card Insertion GPIO This is a GPIO designated by the default software as the Memory Stick card detection pin and has a weak internal pull-up resistor.
MS_INS
IPU
MS_SCLK
13
O8
Memory Stick System Clock This pin is an output clock signal to the MS device.
MS_D[7:0]
20 19 17 18 32 30 23 24
I/O8PD
Memory Stick System Data In/Out These pins are the bi-directional data signals for the MS device. In serial mode, the most significant bit (MSB) of each byte is transmitted first by either the memory stick controller MSC or the MS device on MS_D0. MS_D0, MS_D2, and MS_D3 have weak pull-down resistors. MS_D1 has a pull-down resistor if it is in parallel mode. Otherwise, it is disabled. In 4- or 8-bit parallel modes, all MS_D7 - MS_D0 signals have weak pull-down resistors. xD-PICTURE CARD INTERFACE
xD_D[7:0]
30 32 33 13 17 18 19 20 23
I/O8PD
xD-Picture Card Data 7-0 These pins are the bi-directional data signals xD_D7 - xD_D0 and have weak internal pull-down resistors.
xD_ALE
O8PD
xD-Picture Card Address Strobe This pin is an active high Address Latch Enable (ALE) signal for the xD-Picture Card device. This pin has a weak pull-down resistor that is permanently enabled.
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Table 6.1 USB4640/USB4640i Pin Descriptions (continued) 48-PIN QFN 28 BUFFER TYPE (Table 6.2) IPU
SYMBOL xD_nB/R
DESCRIPTION xD-Picture Card Busy or Data Ready This pin is connected to the BSY/RDY pin of the xD-Picture Card device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal power FET. If an external FET is used (the internal FET is disabled), then the internal pull-up is not available (an external pull-up is required).
xD_nCE
26
O8PU
xD-Picture Card Chip Enable This pin is an active low chip enable signal for the xD-Picture Card device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal power FET. If an external FET is used (internal FET is disabled), then the internal pull-up is not available (an external pull-up is required).
xD_CLE
24
O8PD
xD-Picture Card Command Strobe This pin is an active high Command Latch Enable signal for the xDPicture Card device. This pin has a weak pull-down resistor that is permanently enabled.
GPIO14 /
29
I/O6
This general purpose pin may be used either as input, edge sensitive interrupt input, or output. Custom firmware is required to activate this function. xD-Picture Card Detection GPIO This is a GPIO designated by the default firmware as the xD-Picture Card detection pin and has an internal pull-up.
xD_nCD
I/O8
xD_nRE
27
O8PU
xD-Picture Card Read Enable This pin is an active low read strobe signal for the xD-Picture Card device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal power FET. If an external FET is used (internal FET is disabled), then the internal pull-up is not available (an external pull-up is required).
xD_nWE
22
O8PU
xD-Picture Card Write Enable This pin is an active low write strobe signal for the xD-Picture Card device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal power FET. If an external FET is used (internal FET is disabled), then the internal pull-up is not available (an external pull-up is required).
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Table 6.1 USB4640/USB4640i Pin Descriptions (continued) 48-PIN QFN 21 BUFFER TYPE (Table 6.2) O8PD
SYMBOL xD_nWP
DESCRIPTION xD-Picture Card Write Protect This pin is an active low write protect signal for the xD-Picture Card device. This pin has a weak pull-down resistor that is permanently enabled. SPI INTERFACE
SPI_CE_n
8
O12
SPI Chip Enable This is the active low chip enable output. If the SPI interface is enabled, this pin must be driven high in power down states.
SPI_CLK /
9
I/O12
This is the SPI clock out to the serial ROM. See Section 6.4, "ROM BOOT Sequence" for diagram and usage instructions. During reset, drive this pin low. This pin may be used either as input, edge sensitive interrupt input, or output. Custom firmware is required to activate this function. When configured, this is the I2C EEPROM clock pin.
GPIO4 / SCL SPI_DO / GPIO5 / SDA / SPI_SPD_SEL 10
I/O6
I/O12 I/O6
This is the data out for the SPI port. See Section 6.4, "ROM BOOT Sequence" for diagram and usage instructions. This pin may be used either as input, edge sensitive interrupt input, or output. Custom firmware is required to activate this function. This pin is the data pin when the device is connected to the optional I2C EEPROM.
I/O12
This pin is used to select the speed of the SPI interface. During nRESET assertion, this pin will be tri-stated with the weak pull-down resistor enabled. When nRESET is negated, the value on the pin will be internally latched, and the pin will revert to SPI_DO functionality, the internal pull-down will be disabled. `0' = 30 MHz (No external resistor should be applied.) `1' = 60 MHz (A 10 K external pull-up resistor must be applied.) If the latched value is '1', then the pin is tri-stated when the chip is in the suspend state. If the latched value is '0', then the pin is driven low during a suspend state.
SPI_DI
11
I/O12PD
This is the SPI data in to the controller from the ROM. This pin has a weak internal pull-down applied at all times to prevent floating. MISC
GPIO1 /
37
I/O6
General Purpose I/O This pin may be used either as input, edge sensitive interrupt input, or output. Custom firmware is required to activate this function.
LED / TXD
GPIO1 can be used as an LED output. This signal can be configured as the TXD output of the internal UART. Custom firmware is required to activate this function.
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Table 6.1 USB4640/USB4640i Pin Descriptions (continued) 48-PIN QFN 36 BUFFER TYPE (Table 6.2) I/O6
SYMBOL GPIO2 / RXD GPIO10 (CRD_PWR)
DESCRIPTION This pin may be used either as input, edge sensitive interrupt input, or output. Custom firmware is required to activate this function. This signal can be configured as input to the RXD of the internal UART. Custom firmware is required to activate this function.
35
I/O200
Card power drive: 3.3 V (100 mA or 200 mA) This must be the only FET used to power devices. Failure to do this will violate voltage specifications on device pins. If this pin is not being used as a card power pin, this pin may be used either as input, edge sensitive interrupt input, or output (GPIO). Please see Section 8.4.2.3, "A4h-A5h: Smart Media Device Power Configuration," on page 38 for more information.
nRESET
38
IS
RESET input The system uses this active low signal to reset the chip. The active low pulse should be at least 1 s wide.
TEST
40
I
TEST Input Tie this pin to ground for normal operation. DIGITAL / POWER / GROUND
CRFILT
15
VDD Core Regulator Filter Capacitor This pin requires a 1.0 F (or greater) 20% (ESR <0.1) capacitor to VSS.
PLLFILT
46
Phase-locked Loop Regulator Filter Capacitor This pin requires a 1.0 F (or greater) 20% (ESR <0.1) capacitor to VSS.
VDD12 VDD33
41 5 12 16 25 34 48 ePad
1.2 V Power for HSIC pads and buffers 3.3 V Power and Regulator Input Please see Chapter 10, "DC Parameters," on page 55 for more information. Pins 16 and 48 each require an external bypass capacitor of 4.7 F minimum. The ground pad is the only VSS for the device and must be tied to ground with multiple vias.
VSS
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6.2
BUFFER I I/O IPU IS I/O6 I/OD6PU O8 O8PD O8PU I/O8 I/O8PD I/O8PU O12 I/O12 I/O12PD I/O200 ICLKx OCLKx I/O-U I-R
Buffer Type Descriptions
Table 6.2 USB4640/USB4640i Buffer Type Descriptions DESCRIPTION Input. Input/output. Input with weak internal pull-up. Input with Schmitt trigger. Input/output buffer with 6 mA sink and 6 mA source. Input/open drain output buffer with a 6 mA sink. Output buffer with an 8 mA sink and an 8 mA source. Output buffer with an 8 mA sink and an 8 mA source with a weak internal pull-down resistor. Output buffer with an 8 mA sink and an 8 mA source with a weak internal pull-up resistor. Input/output buffer with an 8 mA sink and an 8 mA source. Input/output buffer with an 8 mA sink and an 8 mA source with a weak internal pull-down resistor. Input/output buffer with an 8 mA sink and an 8 mA source with a weak internal pull-up resistor. Output buffer with a 12 mA sink and a 12 mA source. Input/output buffer with 12 mA sink and 12 mA source. Input/output buffer with 12 mA sink and 12 mA source with a weak internal pull-down resistor. Input/output buffer 12 mA with FET disabled, 100/200 mA source only when the FET is enabled. XTAL clock input. XTAL clock output. Analog input/output as defined in the USB 2.0 Specification. RBIAS.
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6.3
Port Power Control
Port Power control using a USB Power Switch The USB4640/USB4640i has a single port power control and over-current sense signal for each downstream port. When disabling port power, the driver will actively drive a '0'. To avoid unnecessary power dissipation, the internal pull-up resistor will be disabled at that time. When port power is enabled, the output driver is disabled, and the pull-up resistor is enabled creating an open drain output. If there is an over-current situation, the USB Power Switch will assert the open drain OCS signal. The Schmitt trigger input will detect this event as a low. The open drain output does not interfere. The internal over-current sense filter handles the transient conditions, such as low voltage, while the device is powering up.
5V
PRTCTL3
OCS
USB Power Switch
EN
USB4640/40i
USB Device
5V
PRTCTL2
OCS
USB Power Switch
EN
USB Device
Figure 6.1 Port Power Control with USB Power Switch
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Port Power control using a Poly Fuse When using the USB4640/USB4640i with a poly fuse, an external diode must be used (See Figure 6.2). When disabling port power, the USB4640/USB4640i will drive a '0'. This procedure will have no effect since the external diode will isolate the pin from the load. When port power is enabled, the USB4640/USB4640i output driver is disabled, and the pull-up resistor is enabled which creates an open drain output. This open drain output condition means that the pull-up resistor is providing 3.3 volts to the anode of the diode. If there is an over-current situation, the poly fuse will open. This will cause the cathode of the diode to go to zero volts. The anode of the diode will be at 0.7 volts, and the Schmitt trigger input will register this as a low resulting in an over-current detection. The open drain output does not interfere.
5V
PRTCTL3
USB Device
USB4640/40i
PRTCTL2
5V
USB Device
Figure 6.2 Port Power Control with a Single Poly Fuse and Multiple Loads When using a single poly fuse to power all devices, note that for the ganged situation, all power control pins must be tied together.
5V
PRTCTL3
Poly Fuse
USB4640/40i
PRTCTL2
USB Device USB Device
Figure 6.3 Port Power with Ganged Control with Poly Fuse
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6.4
ROM BOOT Sequence
After power-on reset, the internal firmware checks for an external SPI flash device that contains a valid signature of "2DFU" (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and code execution begins at address 0x0000 in the external SPI device. Otherwise, code execution continues from the internal ROM. If there is no SPI ROM detected, the internal firmware then checks for the presence of an I2C ROM. The firmware looks for the signature `ATA2' at the offset of FCh-FFh and `ecf1' at the offset of 17Ch17Fh in the I2C ROM. The firmware reads in the I2C ROM to configure the hardware and software internally. Please refer to Section 8.3.2, "EEPROM Data Descriptor," on page 29 for the details of the configuration options. The SPI ROM required for the USB4640/USB4640i is a recommended minimum of 1 Mbit and support either 30 MHz or 60 MHz. The frequency used is set using the SPI_SPD_SEL. For 30 MHz operation, this pin must be pulled to ground through a 100 k resistor. For 60 MHz operation, this pin must pulled up through a 100 k resistor. The SPI_SPD_SEL pin is used to choose the speed of the SPI interface. During nRESET assertion, this pin will be tri-stated with the weak pull-down resistor enabled. When nRESET is negated, the value on the pin will be internally latched, and the pin will revert to SPI_DO functionality. The internal pulldown will be disabled. The firmware can determine the speed of operation on the SPI port by checking the SPI_SPEED in the SPI_CTL register (0x2400 - RESET = 0x02). Both 1- and 2-bit SPI operation is supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMS are also supported.
SPI_CE_n SPI_CLK / GPIO4 / SCL
CE# CLK SPI ROM SI SO
USB4640/40i
SPI_DO / GPIO5 / SDA / SPI_SPD_SEL SPI_DI
Figure 6.4 SPI ROM Connection
3. 3 V 10 K
SCL
3. 3 V
USB4640/40i
I2C ROM
10 K
SDA
Figure 6.5 I2C Connection
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Chapter 7 Pin Reset States
Hardware Initialization Voltage Signal (v) RESET Firmware Operational
VDD33
RESET
VSS
Time (t)
Figure 7.1 Pin Reset States Table 7.1 Legend for Pin Reset States Table SYMBOL
0 1 IP PU PD none -Z
DESCRIPTION
Output driven low Output driven high Input enabled Hardware enables pull-up Hardware enables pull-down Hardware disables pad Hardware disables function Hardware disables pad. Both output driver and input buffers are disabled.
7.1
Pin Reset States
Table 7.2 USB4640/USB4640i Reset States Table
RESET STATE INPUT/ OUTPUT PU/ PD
PIN
PIN NAME
FUNCTION
1 2 3 4 6 7
USBDN_DM2 USBDN_DP2 USBDN_DM3 USBDN_DP3 PRTCTL2 PRTCTL3
USBDN_DM2 USBDN_DP2 USBDN_DM3 USBDN_DP3 PRTCTL PRTCTL
IP IP IP IP 0 0
PD PD PD PD ---
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Table 7.2 USB4640/USB4640i Reset States Table (continued)
RESET STATE INPUT/ OUTPUT PU/ PD
PIN
PIN NAME
FUNCTION
8 9 10 11 13 14 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 35 36 37 38 39 40
SPI_CE_n SPI_CLK / GPIO4 / SCL SPI_DO / GPIO5 / SDA / SPI_SPD_SEL SPI_DI GPIO6 / SD_WP / MS_SCLK / xD_D4 GPIO15 / SD_nCD SD_D1 / MS_D5 / xD_D3 SD_D0 / MS_D4 / xD_D2 SD_D7 / MS_D6 / xD_D1 SD_D6 / MS_D7 / xD_D0 SD_CLK / MS_BS / xD_nWP xD_nWE SD_D5 / MS_D1 / xD_ALE SD_CMD / MS_D0 / xD_CLE xD_nCE xD_nRE xD_nB/R GPIO14 / xD_nCD SD_D4 / MS_D2 / xD_D7 GPIO12 / MS_INS SD_D3 / MS_D3 / xD_D6 SD_D2 / xD_D5 GPIO10 (CRD_PWR) GPIO2 / RXD GPIO1 / LED / TXD nRESET HSIC_IMP TEST
SPI_CE_n GPIO GPIO SPI_DI GPIO GPIO none none none none none xD_nWE none none xD_nCE xD_nRE xD_nB/R GPIO none GPIO none none GPIO GPIO GPIO nRESET HSIC_IMP TEST
1 0 0 IP 0 IP Z Z Z Z Z Z Z Z Z Z Z IP Z IP Z Z Z 0 0 IP Z IP
---PD -PU -----------PU -PU -------PD
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Table 7.2 USB4640/USB4640i Reset States Table (continued)
RESET STATE INPUT/ OUTPUT PU/ PD
PIN
PIN NAME
FUNCTION
42 43
HSIC_DAT HSIC_STROBE
HSIC_DAT HSIC_STROBE
IP IP
---
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Chapter 8 Configuration Options
8.1 Hub
SMSC's USB 2.0 hub is fully compliant to the Universal Serial Bus Specification available from the USB Implementer's Forum found at http://www.usb.org (Revision 2.0 April 27, 2000 and the 12/7/2000 and 5/28/2002 Errata). Please reference Chapter 11 (Hub Specification) for general details regarding hub operation and functionality. For performance reasons, the hub provides 1 transaction translator (TT) that is shared by both downstream ports defined as a single-TT configuration. The TT contains 4 non-periodic buffers.
8.1.1
Hub Configuration Options
The SMSC hub supports a large number of features (some are mutually exclusive), and must be configured in order to correctly function when attached to a USB host controller. There are two principal ways to configure the hub: via the internal default settings or by settings stored in an external EEPROM or SPI Flash device.
8.1.1.1
Power Switching Polarity
The hub will only support active high power controllers.
8.2
Card Reader
The SMSC USB4640/USB4640i is fully compliant with the following flash media card reader specifications: Secure Digital 2.0 / MultiMediaCard 4.2 -SD 2.0, HS-SD, HC-SD -TransFlashTM and reduced form factor media -1/4/8 bit MMC 4.2 Memory Stick 1.43 Memory Stick Pro Format 1.02 Memory Stick Pro-HG Duo Format 1.01 -Memory Stick, MS Duo, HS-MS, MS Pro-HG, MS Pro Memory Stick Duo 1.10 xD-Picture Card 1.2
8.3
8.3.1
System Configurations
EEPROM/SPI Interface
The USB4640/USB4640i can be configured via a 2-wire (I2C) EEPROM (512x8) or an external SPI flash device containing the firmware for the USB4640/USB4640i. If an external configuration device does not exist the internal default values will be used. If one of the external devices is used for configuration, the OEM can update the values through the USB interface. The hub will then "attach" to the upstream USB host.
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The USBDM tool set is available in the USB264x Hub Card reader combo software release package. To download the software package from SMSC's website, please visit: https://www2.smsc.com/mkt/CW_SFT_PUB.nsf/Agreements/OBJ+Hub+Card+Reader to go to the OBJ Hub Card Reader Software Download Agreement. Review the license, and if you agree, check the "I agree" box and then select "Confirm". You will then be able to download USB264x Hub Card reader combo release package zip file containing the USBDM tool set. Please note that the following applies to the system values and descriptions when used: N/A = Not applicable to this part Reserved = For internal use
8.3.2
EEPROM Data Descriptor
Table 8.1 Internal Flash Media Controller Configurations
ADDRESS 00h 01h 02h-19h 1Ah-1Bh 1Ch-1Dh 1Eh 1Fh 20h 21h 22h 23h 24h-31h 32h-5Dh 5Eh 5Fh 60h-99h 9Ah
REGISTER NAME USB_SER_LEN USB_SER_TYP USB_SER_NUM USB_VID USB_PID USB_LANG_LEN USB_LANG_TYP USB_LANG_ID_LSB USB_LANG_ID_MSB USB_MFR_STR_LEN USB_MFR_STR_TYP USB_MFR_STR Reserved USB_PRD_STR_LEN USB_PRD_STR_TYP USB_PRD_STR USB_BM_ATT
DESCRIPTION USB Serial String Descriptor Length USB Serial String Descriptor Type USB Serial Number USB Vendor Identifier USB Product Identifier USB Language String Descriptor Length USB Language String Descriptor Type USB Language Identifier Least Significant Byte USB Language Identifier Most Significant Byte USB Manufacturer String Descriptor Length USB Manufacturer String Descriptor Type USB Manufacturer String USB Product String Descriptor Length USB Product String Descriptor Type USB Product String USB BmAttribute
29
INTERNAL DEFAULT VALUE 1Ah 03h "000008264001" (See Note 8.1) 0424 4040 04h 03h 09h (See Note 8.3) 04h (See Note 8.3) 10h 03h "Generic" (See Note 8.1) 00h 30h 03h "Ultra Fast Media Reader" (See Note 8.1) 80h
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Table 8.1 Internal Flash Media Controller Configurations (continued) ADDRESS 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h-A3h A4h A5h A6h A7h A8h A9h AAh - B0h B1h - B7h B8h - BEh BFh - C5h C6h - CDh CEh - D2h D3h D4h - D7h D8h - DAh DBh - DDh REGISTER NAME USB_MAX_PWR ATT_LB ATT_HLB ATT_LHB ATT_HB MS_PWR_LB MS_PWR_HB Not Applicable SM_PWR_LB SM_PWR_HB SD_PWR_LB SD_PWR_HB LED_BLK_INT LED_BLK_DUR DEV0_ID_STR DEV1_ID_STR DEV2_ID_STR DEV3_ID_STR INQ_VEN_STR INQ_PRD_STR DYN_NUM_LUN DEV_LUN_MAP Reserved Reserved DESCRIPTION USB Max Power Attribute Lo byte Attribute Hi Lo byte Attribute Lo Hi byte Attribute Hi byte Memory Stick Device Power Lo byte Memory Stick Device Power Hi byte Smart Media Device Power Lo byte Smart Media Device Power Hi byte Secure Digital Device Power Lo byte Secure Digital Device Power Hi byte LED Blink Interval LED Blink After Access Device 0 Identifier String Device 1 Identifier String Device 2 Identifier String Device 3 Identifier String Inquiry Vendor String Inquiry Product String Dynamic Number of LUNs Device to LUN Mapping INTERNAL DEFAULT VALUE 30h (96 mA) 40h (Reverse SD_WP only) 80h (Reverse SD2_WP only) 00h 00h 00h 0Ah 00h 00h (See Note 8.2) 0Ah (See Note 8.2) 00h 0Ah 02h 28h N/A "MS" "SM" (See Note 8.2) "SD/MMC" "Generic" 82640 01h FFh, 00h, 00h, 00h 00h, 06h, 0Dh 59h, 56h, 97h
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Table 8.2 Hub Controller Configurations ADDRESS DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h REGISTER NAME VID_LSB VID_MSB PID_LSB PID_MSB DID_LSB DID_MSB CFG_DAT_BYT1 CFG_DAT_BYT2 CFG_DAT_BYT3 NR_DEVICE PORT_DIS_SP PORT_DIS_BP MAX_PWR_SP MAX_PWR_BP HC_MAX_C_SP HC_MAX_C_BP PWR_ON_TIME BOOST_UP BOOST_3:0 PRT_SWP PRTM12 PRTM3 DESCRIPTION Vendor ID Least Significant Byte Vendor ID Most Significant Byte Product ID Least Significant Byte Product ID Most Significant Byte Device ID Least Significant Byte Device ID Most Significant Byte Configuration Data Byte 1 Configuration Data Byte 2 Configuration Data Byte 3 Non-Removable Devices Port Disable (Self) Port Disable (Bus) Max Power (Self) Max Power (Bus) Hub Controller Max Current (Self) Hub Controller Max Current (Bus) Power-on Time Boost_Up Boost_3:0 Port Swap Port Map 12 Port Map 3 Table 8.3 Other Internal Configurations ADDRESS F4h F5h F6h F7-FAh FBh FCh-FFh REGISTER NAME Reserved Reserved Reserved Not Applicable Not Applicable NVSTORE_SIG DESCRIPTION Reserved Reserved Reserved Non-Volatile Storage Signature INTERNAL DEFAULT VALUE 00h 66h 00h N/A 00h "ATA2" INTERNAL DEFAULT VALUE 24h 04h 40h 26h A1h 08h 8Bh 28h 00h 02h 00h 00h 01h 32h 01h 32h 32h 00h 00h 00h 00h 00h
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8.4
Set bit 7 of bmAttribute to enable the registers in Table 8.4.
Table 8.4 Internal Flash Media Controller Extended Configurations
ADDRESS 100h - 106h 107h- 129h 12Ah-145h 146h 147h - 14Bh 14Ch 14Dh-17Bh 17Ch-17Fh
REGISTER NAME CLUN0_ID_STR Not Applicable Not applicable Not Applicable Not Applicable Not Applicable Not Applicable NVSTORE_SIG2 Note 8.1
DESCRIPTION Combo LUN 0 Identifier String Non-Volatile Storage Signature
INTERNAL DEFAULT VALUE "COMBO" N/A 00h 01h 01h, FFh, FFh, FFh, FFh 0Ah 00h "ecf1"
This value is a UNICODE UTF-16LE encoded string value that meets the USB 2.0 specification (Revision 2.0, 2000). Values in double quotations without this note are ASCII values. A value of "SM" will be overridden with "xD" once an xD-Picture Card has been identified. For a list of the most current 16-bit language ID's defined by the USB-IF, please visit http://www.unicode.org or consult The Unicode Standard, Worldwide Character Encoding, (Version 4.0), The Unicode Consortium, Addison-Wesley Publishing Company, Reading, Massachusetts.
Note 8.2 Note 8.3
8.4.1
8.4.1.1
BYTE 0
EEPROM Data Descriptor Register Descriptions
00h: USB Serial String Descriptor Length
NAME USB_SER_LEN DESCRIPTION USB serial string descriptor length as defined by Section 9.6.7 "String" of the USB 2.0 Specification (Revision 2.0, 2000). This field is the "bLength" which describes the size of the string descriptor (in bytes).
8.4.1.2
BYTE 1
01h: USB Serial String Descriptor Type
NAME USB_SER_TYP DESCRIPTION USB serial string descriptor type as defined by Section 9.6.7 "String" of the USB 2.0 Specification (Revision 2.0, 2000). This field is the "bDescriptorType" which is a constant value associated with a string descriptor type.
8.4.1.3
BYTE 25:2
02h-19h: USB Serial Number Option
NAME USB_SER_NUM DESCRIPTION Maximum string length is 12 hex digits. Must be unique to each device.
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8.4.1.4
BYTE 1:0
1Ah-1Bh: USB Vendor ID Option
NAME USB_VID DESCRIPTION This ID is unique for every vendor. The vendor ID is assigned by the USB Implementer's Forum.
8.4.1.5
BYTE 1:0
1Ch-1Dh: USB Product ID Option
NAME USB_PID DESCRIPTION This ID is unique for every product. The product ID is assigned by the vendor.
8.4.1.6
BYTE 0
1Eh: USB Language Identifier Descriptor Length
NAME USB_LANG_LEN DESCRIPTION USB language ID string descriptor length as defined by Section 9.6.7 "String" of the USB 2.0 Specification (Revision 2.0, 2000). This field is the "bLength" which describes the size of the string descriptor (in bytes).
8.4.1.7
BYTE 1
1Fh: USB Language Identifier Descriptor Type
NAME USB_LANG_TYP DESCRIPTION USB language ID string descriptor type as defined by Section 9.6.7 "String" of the USB 2.0 Specification (Revision 2.0, 2000). This field is the "bDescriptorType" which is a constant value associated with a string descriptor type.
8.4.1.8
BYTE 2
20h: USB Language Identifier Least Significant Byte
NAME USB_LANG_ID _LSB DESCRIPTION English language code = `0409'. See Note 8.3 to reference additional language ID's defined by the USB-IF.
8.4.1.9
BYTE 3
21h: USB Language Identifier Most Significant Byte
NAME USB_LANG_ID _MSB DESCRIPTION English language code = `0409'. See Note 8.3 to reference additional language ID's defined by the USB-IF.
8.4.1.10
BYTE 0
22h: USB Manufacturer String Descriptor Length
NAME USB_MFR_STR _LEN DESCRIPTION USB manufacturer string descriptor length as defined by Section 9.6.7 "String" of the USB 2.0 Specification (Revision 2.0, 2000). This field is the "bLength" which describes the size of the string descriptor (in bytes).
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8.4.1.11
BYTE 1
23h: USB Manufacturer String Descriptor Type
NAME USB_MFR_STR _TYP DESCRIPTION USB manufacturer string descriptor type as defined by Section 9.6.7 "String" of the USB 2.0 Specification (Revision 2.0, 2000). This field is the "bDescriptorType" which is a constant value associated with a string descriptor type.
8.4.1.12
BYTE 15:2
24h-31h: USB Manufacturer String Option
NAME USB_MFR_STR DESCRIPTION The maximum string length is 28 characters.
8.4.1.13
BYTE 59:16
32h-5Dh: Reserved
NAME Reserved Reserved. DESCRIPTION
8.4.1.14
BYTE 0
5Eh: USB Product String Descriptor Length
NAME USB_PRD_STR _LEN DESCRIPTION USB product string descriptor length as defined by Section 9.6.7 "String" of the USB 2.0 Specification (Revision 2.0, 2000). This field is the "bLength" which describes the size of the string descriptor (in bytes).
8.4.1.15
BYTE 1
5Fh: USB Product String Descriptor Type
NAME USB_PRD_STR _TYP DESCRIPTION USB product string descriptor type as defined by Section 9.6.7 "String" of the USB 2.0 Specification (Revision 2.0, 2000). This field is the "bDescriptorType" which is a constant value associated with a string descriptor type.
8.4.1.16
BYTE 59:2
60h-99h: USB Product String Option
NAME USB_PRD_STR DESCRIPTION This string will be used during the USB enumeration process in the Windows(R) operating system. Maximum string length is 28 characters.
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8.4.1.17
BIT 7:0
9Ah: USB BmAttribute (1 byte)
NAME USB_BM_ATT DESCRIPTION Self- or Bus-Power: Selects between self- and bus-powered operation. The hub is either self-powered (draws less than 2 mA) or bus-powered (limited to 100 mA maximum power prior to being configured by the host controller). When configured as a bus-powered device, the SMSC hub consumes less than 100 mA of current prior to being configured. After configuration, the buspowered SMSC hub (along with all associated hub circuitry, any embedded devices if part of a compound device, and 100 mA per externally available downstream port) must consume no more than 500 mA of current. The current consumption is system dependent, and the OEM must ensure that the USB 2.0 Specification is not violated. When configured as a self-powered device, <1 mA of current is consumed and all ports are available, with each port being capable of sourcing 500 mA of current. 80 = Bus-powered operation (default) C0 = Self-powered operation A0 = Bus-powered operation with remote wake-up E0 = Self-powered operation with remote wake-up
8.4.1.18
BIT 7:0
9Bh: USB MaxPower (1 byte)
NAME USB_MAX_PWR DESCRIPTION USB Max Power per the USB 2.0 Specification. Do NOT set this value greater than 100 mA.
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8.4.1.19
9Ch-9Fh: Attribute Byte Descriptions
BYTE NAME ATT_LB
BYTE 0
BIT 3:0 4 Always reads `0'.
DESCRIPTION
Inquire Manufacturer and Product ID Strings `1' - Use the Inquiry Manufacturer and Product ID Strings. `0' (default) - Use the USB Descriptor Manufacturer and Product ID Strings.
5 6
Always reads `0'. Reverse SD Card Write Protect Sense `1' (default) - SD cards will be write protected when SW_nWP is high, and writable when SW_nWP is low. `0' - SD cards will be write protected when SW_nWP is low, and writable when SW_nWP is high.
7
Extended Configuration Enable '1' - This bit must be set to '1' to enable editing, updating, and reading from registers 100h-17Fh. '0' - The internal configuration is loaded. When this bit is not set (and it equals '0'). It will not read from registers 100h-17Fh.
1
ATT_HLB
3:0 4
Always reads `0'. Activity LED True Polarity `1' - Activity LED to Low True. `0' (default) - Activity LED polarity to High True.
5
Common Media Insert / Media Activity LED `1' - The activity LED will function as a common media inserted/media access LED. `0' (default) - The activity LED will remain in its idle state until media is accessed.
6 7
Always reads `0'. Reverse SD2 Card Write Protect Sense `1' (default) - SD cards in LUN 1 will be write protected when SW_nWP is high, and writable when SW_nWP is low. `0' - SD cards in LUN 1 will be write protected when SW_nWP is low, and writable when SW_nWP is high.
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BYTE 2
BYTE NAME ATT_LHB
BIT 0
DESCRIPTION Attach on Card Insert / Detach on Card Removal `1' - Attach on Insert is enabled. `0' (default) - Attach on Insert is disabled.
1 2
Always reads `0'. Enable Device Power Configuration `1' - Custom Device Power Configuration stored in the NVSTORE is used. `0' (default) - Default Device Power Configuration is used.
7:3 3 ATT_HB 6:0 7
Always reads `0'. Always reads `0'. xD Player Mode
8.4.2
A0h-A7h: Device Power Configuration
The USB4640/USB4640i has one internal FET which can be utilized for card power. This section describes the default internal configuration. The settings are stored in NVSTORE and provide the following features: 1. A card can be powered by an external FET or by an internal FET. 2. The power limit can be set to 100 mA or 200 mA (Default) for the internal FET. Each media uses two bytes to store its device power configuration. Bit 3 selects between internal or external card power FET options. For internal FET card power control, bits 0 through 2 are used to set the power limit. The "Device Power Configuration" bits are ignored unless the "Enable Device Power Configuration" bit is set. See Section 8.4.1.19, "9Ch-9Fh: Attribute Byte Descriptions," on page 36.
8.4.2.1
A0h-A1h: Memory Stick Device Power Configuration
FET 0 1 2
TYPE FET Lo Byte MS_PWR_LB FET Hi Byte MS_PWR_HB
BITS 3:0 7:4 3:0
BIT TYPE Low Nibble High Nibble Low Nibble 0000b 0001b 1000b 1010b 0000b Disabled
DESCRIPTION
Disabled External FET enabled Internal FET with 100 mA power limit Internal FET with 200 mA power limit
3
7:4
High Nibble
0000b Disabled
8.4.2.2
BYTE 1:0
A2h-A3h: Not Applicable
NAME Not Applicable Not applicable. DESCRIPTION
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8.4.2.3
A4h-A5h: Smart Media Device Power Configuration
FET 0 1 2
TYPE FET Lo Byte SM_PWR_LB FET Hi Byte SM_PWR_HB
BITS 3:0 7:4 3:0
BIT TYPE Low Nibble High Nibble Low Nibble 0000b 0001b 1000b 1010b 0000b Disabled
DESCRIPTION
Disabled External FET enabled Internal FET with 100 mA power limit Internal FET with 200 mA power limit
3
7:4
High Nibble
0000b Disabled
8.4.2.4
A6h-A7h: Secure Digital Device Power Configuration
FET 0 1 2
TYPE FET Lo Byte SD_PWR_LB FET Hi Byte SD_PWR_HB
BITS 3:0 7:4 3:0
BIT TYPE Low Nibble High Nibble Low Nibble 0000b 0001b 1000b 1010b 0000b Disabled
DESCRIPTION
Disabled External FET enabled Internal FET with 100 mA power limit Internal FET with 200 mA power limit
3
7:4
High Nibble
0000b Disabled
8.4.2.5
BYTE 0
A8h: LED Blink Interval
NAME LED_BLK_INT DESCRIPTION The blink rate is programmable in 50 ms intervals. The high bit (7) indicates an idle state: `0' - Off `1' - On The remaining bits (6:0) are used to determine the blink interval up to a max of 128 x 50 ms.
8.4.2.6
BYTE 1
A9h: LED Blink Duration
NAME LED_BLK_DUR DESCRIPTION LED Blink After Access. This byte is used to designate the number of seconds that the GPIO1 LED will continue to blink after a drive access. Setting this byte to "05" will cause the GPIO 1 LED to blink for 5 seconds after a drive access.
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8.4.3
Device ID Strings
These bytes are used to specify the LUN descriptor returned by the device. These bytes are used in combination with the device to LUN mapping bytes in applications where the OEM wishes to reorder and rename the LUNs. If multiple devices are mapped to the same LUN (a COMBO LUN), then the CLUN#_ID_STR will be used to name the COMBO LUN instead of the individual device strings. When applicable, the "SM" value will be overridden with xD once an xD-Picture Card has been identified.
8.4.3.1
BYTE 6:0
AAh-B0h: Device 0 Identifier String
NAME DEV0_ID_STR Not applicable. DESCRIPTION
8.4.3.2
BYTE 6:0
B1h-B7h: Device 1 Identifier String
NAME DEV1_ID_STR DESCRIPTION This ID string is associated with the Memory Stick device.
8.4.3.3
BYTE 6:0
B8h-BEh: Device 2 Identifier String
NAME DEV2_ID_STR DESCRIPTION This ID string is associated with the Smart Media (Note 8.2) device.
8.4.3.4
BYTE 6:0
BFh-C5h: Device 3 Identifier String
NAME DEV3_ID_STR DESCRIPTION This ID string is associated with the Secure Digital / MultiMediaCard device.
8.4.3.5
BYTE 7:0
C6h-CDh: Inquiry Vendor String
NAME INQ_VEN_STR DESCRIPTION If bit 4 of the 1st attribute byte is set, the device will use these strings in response to a USB inquiry command, instead of the USB descriptor manufacturer and product ID strings.
8.4.3.6
BYTE 4:0
CEh-D2h: Inquiry Product String
NAME INQ_PRD_STR DESCRIPTION If bit 4 of the 1st attribute byte is set, the device will use these strings in response to a USB inquiry command, instead of the USB descriptor manufacturer and product ID strings.
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8.4.3.7
BIT 7:0
D3h: Dynamic Number of LUNs
NAME DYN_NUM_LUN DESCRIPTION These bytes are used to specify the number of LUNs the device exposes to the host. These bytes are also used for icon sharing by assigning more than one LUN to a single icon. This is used in applications where the device utilizes a combo socket and the OEM wishes to have only a single icon displayed for one or more interfaces. If this field is set to "FF", the program assumes that you are using the default value and icons will be configured per the default configuration.
8.4.3.8
BYTE 3:0
D4h-D7h: Device to LUN Mapping
NAME DEV_LUN_MAP DESCRIPTION These registers map a device controller (SD/MMC, SM (Note 8.2), and MS) to a Logical Unit Number (LUN). The device reports the mapped LUNs to the USB host in the USB descriptor during enumeration. The icon installer associates custom icons with the LUNs specified in these fields. Setting a register to "FF" indicates that the device is not mapped. Setting all of the DEV_LUN_MAP registers for all devices to "FF" forces the use of the default mapping configuration. Not all configurations are valid. Valid configurations depend on the hardware, packaging, and OEM board layout. The number of unique LUNs mapped must match the value in the Section 8.4.3.7, "D3h: Dynamic Number of LUNs," on page 40.
8.4.3.9
BYTE 2:0
D8h-DDh: Reserved
NAME Reserved Reserved. DESCRIPTION
8.4.4
8.4.4.1
BIT 7:0
Hub Controller Configurations
DEh: Vendor ID (LSB)
BYTE NAME VID_LSB DESCRIPTION Least Significant Byte of the Vendor ID. This is a 16-bit value that uniquely identifies the vendor of the user device (assigned by USB Implementer's Forum).
8.4.4.2
BIT 7:0
DFh: Vendor ID (MSB)
BYTE NAME VID_MSB DESCRIPTION Most Significant Byte of the Vendor ID. This is a 16-bit value that uniquely identifies the vendor of the user device (assigned by USB Implementer's Forum).
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8.4.4.3
BIT 7:0
E0h: Product ID (LSB)
NAME PID_LSB DESCRIPTION Least Significant Byte of the Product ID. This is a 16-bit value that the vendor can assign that uniquely identifies this particular product.
8.4.4.4
BIT 7:0
E1h: Product ID (MSB)
NAME PID_MSB DESCRIPTION Most Significant Byte of the Product ID. This is a 16-bit value that the vendor can assign that uniquely identifies this particular product.
8.4.4.5
BIT 7:0
E2h: Device ID (LSB)
NAME DID_LSB DESCRIPTION Least Significant Byte of the Device ID. This is a 16-bit device release number in BCD (binary coded decimal) format.
8.4.4.6
BIT 7:0
E3h: Device ID (MSB)
NAME DID_MSB DESCRIPTION Most Significant Byte of the Device ID. This is a 16-bit device release number in BCD format.
8.4.4.7
BIT 7
E4h: Configuration Data Byte 1 (CFG_DAT_BYT1)
NAME SELF_BUS_PWR DESCRIPTION Self- or Bus-Power: Selects between self- and bus-powered operation. The hub is either self-powered (draws less than 2 mA) or bus-powered (limited to 100 mA maximum power prior to being configured by the host controller). When configured as a bus-powered device, the SMSC hub consumes less than 100 mA of current prior to being configured. After configuration, the buspowered SMSC hub (along with all associated hub circuitry, any embedded devices if part of a compound device, and 100 mA per externally available downstream port) must consume no more than 500 mA of current. The current consumption is system dependent, and the OEM must ensure that the USB 2.0 specifications are not violated. When configured as a self-powered device, <1 mA of current is consumed and all ports are available, with each port being capable of sourcing 500 mA of current. `0' = Bus-powered operation `1' = Self-powered operation
6 5
Reserved HS_DISABLE
Reserved Hi-Speed Disable: Disables the capability to attach as either a Hi-/Full-Speed device, and forces attachment as Full-Speed only (i.e. no Hi-Speed support). `0' = Hi-/Full-Speed `1' = Full-Speed-Only (Hi-Speed disabled!)
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BIT 4:3 2:1
NAME Reserved CURRENT_SNS Reserved
DESCRIPTION
Over-Current Sense: Selects current sensing on a port-by-port basis, all ports ganged, or none (only for bus-powered hubs). The ability to support current sensing on a per port or ganged basis is dependent upon the hardware implementation. `00' = Ganged sensing (all ports together) `01' = Individual (port-by-port) `1x' = Over-current sensing not supported (must only be used with buspowered configurations!)
0
PORT_PWR
Port Power Switching: Enables power switching on all ports simultaneously (ganged), or port power is individually switched on and off on a port-by-port basis (individual). The ability to support power enabling on a port or ganged basis is dependent upon the hardware implementation. `0' = Ganged switching (all ports together) `1' = Individual port-by-port switching
8.4.4.8
BIT 7:6 5:4
E5h: Configuration Data Byte 2 (CFG_DAT_BYT2)
NAME Reserved OC_TIMER Reserved OverCurrent Timer: Over-current timer delay. `00' = 50 ns `01' = 100 ns `10' = 200 ns `11' = 400 ns DESCRIPTION
3
COMPOUND
Compound Device: Allows OEM to indicate that the hub is part of a compound device (per the USB 2.0 Specification). The applicable port(s) must also be defined as having a "non-removable device". Note: When configured via strapping options, declaring a port as nonremovable automatically causes the hub controller to report that it is part of a compound device.
`0' = No `1' = Yes, the hub is part of a compound device 2:0 Reserved Reserved
8.4.4.9
BIT 7:4
E6h: Configuration Data Byte 3 (CFG_DAT_BYT3)
NAME Reserved Reserved DESCRIPTION
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BIT 3
NAME PRTMAP_EN
DESCRIPTION Port Mapping Enable: Selects the method used by the hub to assign port numbers and disable ports. `0' = Standard Mode. Strap options or the following registers are used to define which ports are enabled, and the ports are mapped as port `n' on the hub is reported as port `n' to the host, unless one of the ports is disabled, then the higher numbered ports are remapped in order to report contiguous port numbers to the host. Register 300Ah: Port disable for self-powered operation (Reset = 0x00). Register 300Bh: Port disable for bus-powered operation (Reset = 0x00). `1' = Port Map mode. The mode enables remapping via the registers defined below. Register 30FBh: Port Map 12 (Reset = 0x00) Register 30FCh: Port Map 3 (Reset = 0x00)
2:0
Reserved
Reserved
8.4.4.10
BIT 7:0
E7h: Non-Removable Device
BYTE NAME NR_DEVICE DESCRIPTION Indicates which port(s) include non-removable devices. `0' = Port is removable `1' = Port is non-removable Informs the host if one of the active ports has a permanent device that is undetachable from the hub. The device must provide its own descriptor data. When using the internal default option, the NON_REM[1:0] pins will designate the appropriate ports as being non-removable. Bit Bit Bit Bit Bit Bit Bit Bit 7= 6= 5= 4= 3= 2= 1= 0= Reserved Reserved Reserved Reserved Controls physical port 3 Controls physical port 2 Controls physical port 1 Reserved Bit 1 must be set to a `1' by the firmware for proper identification of the card reader as a non-removable device.
Note:
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8.4.4.11
BIT 7:0
E8h: Port Disable For Self-Powered Operation
BYTE NAME PORT_DIS_SP Disables 1 or more ports. `0' = Port is available `1' = Port is disabled During self-powered operation this register selects the ports which will be permanently disabled. The ports are unavailable to be enabled or enumerated by a host controller. The ports can be disabled in any order since the internal logic will automatically report the correct number of enabled ports to the USB host and will reorder the active ports in order to ensure proper function. Bit Bit Bit Bit Bit Bit Bit Bit 7= 6= 5= 4= 3= 2= 1= 0= Reserved Reserved Reserved Reserved Controls physical port 3 Controls physical port 2 Controls physical port 1 Reserved DESCRIPTION
8.4.4.12
BIT 7:0
E9h: Port Disable For Bus-Powered Operation
BYTE NAME PORT_DIS_BP Disables 1 or more ports. `0' = Port is available `1' = Port is disabled During self-powered operation, this register selects the ports which will be permanently disabled. The ports are unavailable to be enabled or enumerated by a host controller. The ports can be disabled in any order, the internal logic will automatically report the correct number of enabled ports to the USB host and will reorder the active ports in order to ensure proper function. When using the internal default option, the PRT_DIS[1:0] pins will disable the appropriate ports. Bit Bit Bit Bit Bit Bit Bit Bit 7= Reserved 6= Reserved 5= Reserved 4= Reserved 3= Controls physical port 3 2= Controls physical port 2 1= Controls physical port 1 0 is Reserved DESCRIPTION
8.4.4.13
BIT 7:0
EAh: Max Power For Self-Powered Operation
BYTE NAME MAX_PWR_SP DESCRIPTION Value in 2 mA increments that the hub consumes when operating as a selfpowered hub. This value includes the hub silicon along with the combined power consumption of all associated circuitry on the board. This value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0 mA in its descriptors. Note: The USB 2.0 Specification does not permit this value to exceed 100 mA.
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8.4.4.14
BIT 7:0
EBh: Max Power For Bus-Powered Operation
BYTE NAME MAX_PWR_BP DESCRIPTION Value in 2 mA increments that the hub consumes when operating as a buspowered hub. This value includes the hub silicon along with the combined power consumption of all associated circuitry on the board. This value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0 mA in its descriptors.
8.4.4.15
BIT 7:0
ECh: Hub Controller Max Current For Self-Powered Operation
BYTE NAME HC_MAX_C_SP DESCRIPTION Value in 2 mA increments that the hub consumes when operating as a selfpowered hub. This value includes the hub silicon along with the combined power consumption of all associated circuitry on the board. This value does NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound device. Note: The USB 2.0 Specification does not permit this value to exceed 100 mA.
A value of 50 (decimal) indicates 100 mA, which is the default value.
8.4.4.16
BIT 7:0
EDh: Hub Controller Max Current For Bus-Powered Operation
BYTE NAME HC_MAX_C_BP DESCRIPTION Value in 2 mA increments that the hub consumes when operating as a buspowered hub. This value will include the hub silicon along with the combined power consumption of all associated circuitry on the board. This value will NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound device. A value of 50 (decimal) would indicate 100 mA, which is the default value.
8.4.4.17
BIT 7:0
EEh: Power-On Time
BYTE NAME PWR_ON_TIME DESCRIPTION The length of time that it takes (in 2 ms intervals) from the time the host initiated power-on sequence begins on a port until power is adequate on that port. If the host requests the power-on time, the system software uses this value to determine how long to wait before accessing a powered-on port.
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8.4.4.18
BIT 7:2 1:0
EFh: Boost_Up
NAME Reserved BOOST_IOUT Reserved USB electrical signaling drive strength boost bit for the upstream port `A'. `00' = Normal electrical drive strength = No boost `01' = Elevated electrical drive strength = Low (approximately 4% boost) `10' = Elevated electrical drive strength = Medium (approximately 8% boost) `11' = Elevated electrical drive strength = High (approximately 12% boost) Note: "Boost" could result in non-USB compliant parameters. OEM should use a `00' value unless specific implementation issues require additional signal boosting to correct for degraded USB signaling levels. DESCRIPTION
8.4.4.19
BIT 7:6 5:4
F0h: Boost_3:0
NAME Reserved BOOST_IOUT_3 Reserved Upstream USB electrical signaling drive strength boost bit for downstream port `3'. `00' = Normal electrical drive strength = No boost `01' = Elevated electrical drive strength = Low (approximately 4% boost) `10' = Elevated electrical drive strength = Medium (approximately 8% boost) `11' = Elevated electrical drive strength = High (approximately 12% boost) DESCRIPTION
3:2
BOOST_IOUT_2
Upstream USB electrical signaling drive strength boost bit for downstream port `2'. `00' = Normal electrical drive strength = No boost `01' = Elevated electrical drive strength = Low (approximately 4% boost) `10' = Elevated electrical drive strength = Medium (approximately 8% boost) `11' = Elevated electrical drive strength = High (approximately 12% boost) Note: "Boost" could result in non-USB Compliant parameters. OEM should use a `00' value unless specific implementation issues require additional signal boosting to correct for degraded USB signaling levels.
1:0
Reserved
Always reads `0'.
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8.4.4.20
BIT 7:0
F1h: Port Swap
BYTE NAME PRT_SWP DESCRIPTION Swaps the upstream and downstream USB DP and DM pins for ease of board routing to devices and connectors. `0' = USB D+ functionality is associated with the DP pin and D- functionality is associated with the DM pin. `1' = USB D+ functionality is associated with the DM pin and D- functionality is associated with the DP pin. Bit Bit Bit Bit Bit Bit Bit Bit 7= 6= 5= 4= 3= 2= 1= 0= Reserved Reserved Reserved Reserved Controls physical port 3 Controls physical port 2 Reserved Controls physical port 0
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8.4.4.21
BIT 7:0
F2h: Port Map 12
BYTE NAME PRTM12 DESCRIPTION PortMap register for ports 1 & 2 When a hub is enumerated by a USB host controller, the hub is only permitted to report how many ports it has; the hub is not permitted to select a numerical range or assignment. The host controller will number the downstream ports of the hub starting with the number '1', up to the number of ports that the hub reported having. The host's port number is referred to as "logical port number" and the physical port on the hub is the "physical port number". When remapping mode is enabled (see PRTMAP_EN in Register 08h: Configuration Data Byte 3) the hub's downstream port numbers can be remapped to different logical port numbers (assigned by the host). Note: The OEM must ensure that contiguous logical port numbers are used, starting from number `1' up to the maximum number of enabled ports; this ensures that the hub's ports are numbered in accordance with the way a host will communicate with the ports. Table 8.5 Port Map Register for Ports 1 & 2 Bit [7:4] `0000' `0001' `0010' `0011' `0100' to `1111' Bit [3:0] `0000' `0001' `0010' `0011' `0100' to `1111' Physical port 2 is disabled Physical port 2 is mapped to Logical port 1 Physical port 2 is mapped to Logical port 2 Physical port 2 is mapped to Logical port 3 Illegal; Do not use
Physical port 1 is disabled Physical port 1 is mapped to Logical port 1 Physical port 1 is mapped to Logical port 2 Physical port 1 is mapped to Logical port 3 Illegal; Do not use
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8.4.4.22
BIT 7:0
F3h: Port Map 3
BYTE NAME PRTM3 PortMap register for port 3. When a hub is enumerated by a USB host controller, the hub is only permitted to report how many ports it has; the hub is not permitted to select a numerical range or assignment. The host controller will number the downstream ports of the hub starting with the number '1', up to the number of ports that the hub reported having. The host's port number is referred to as "logical port number" and the physical port on the hub is the "physical port number". When remapping mode is enabled (see PRTMAP_EN in Register 08h: Configuration Data Byte 3) the hub's downstream port numbers can be remapped to different logical port numbers (assigned by the host). Note: The OEM must ensure that contiguous logical port numbers are used, starting from number `1' up to the maximum number of enabled ports; this ensures that the hub's ports are numbered in accordance with the way a host will communicate with the ports. Table 8.6 Port Map Register for Port 3 Bit [7:4] `0000' `0001' `0010' `0011' `0100' to `1111' Bit [3:0] `0000' `0001' `0010' `0011' `0100' to `1111' Reserved Reserved Reserved Reserved Illegal; Do not use DESCRIPTION
Physical port 3 is disabled Physical port 3 is mapped to Logical port 1 Physical port 3 is mapped to Logical port 2 Physical port 3 is mapped to Logical port 3 Illegal; Do not use
8.4.4.23
BYTE 6:0
F4h-F6h: Reserved
BYTE NAME Reserved Reserved. DESCRIPTION
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8.4.4.24
BIT 7:0
F7h-FBh: Not Applicable
BYTE NAME Not Applicable Not applicable. DESCRIPTION
8.4.4.25
BYTE 3:0
FCh-FFh: Non-Volatile Storage Signature
NAME NVSTORE_SIG DESCRIPTION This signature is used to verify the validity of the data in the first 256 bytes of the configuration area. The signature must be set to `ATA2' for USB4640/USB4640i.
8.4.5
Internal Flash Media Controller Extended Configurations
Enable Registers 100h - 17Fh by setting bit 7 of bmAttribute.
8.4.5.1
BYTE 6:0
100h-106h: Combo LUN 0 Identifier String
NAME CLUN0_ID_STR DESCRIPTION If the device to LUN mapping bytes have configured this LUN to be a combo LUN, then these strings will be used to identify the LUN rather than the device identifier strings.
8.4.5.2
BYTE 116:0
107h-17Bh: Not Applicable
NAME Not Applicable Not Applicable. DESCRIPTION
8.4.5.3
BYTE 3:0
17Ch -17Fh: Non-Volatile Storage Signature for Extended Configuration
NAME NVSTORE_SIG2 DESCRIPTION This signature is used to verify the validity of the data in the upper 256 bytes if a 512 byte EEPROM is used, otherwise this bank is a read-only configuration area. The signature must be set to 'ecf1'.
8.4.6
I2C EEPROM
The I2C EEPROM interface implements a subset of the I2C Master Specification (Please refer to the Philips Semiconductor Standard I2C-Bus Specification for details on I2C bus protocols). The device's I2C EEPROM interface is designed to attach to a single "dedicated" I2C EEPROM, and it conforms to the Standard-mode I2C Specification (100 kbps transfer rate and 7-bit addressing) for protocol and electrical compatibility. Note: Extensions to the I2C Specification are not supported. The device acts as the master and generates the serial clock SCL, controls the bus access (determines which device acts as the transmitter and which device acts as the receiver), and generates the START and STOP conditions.
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8.4.6.1
Implementation Characteristics
The device will only access an EEPROM using the sequential read protocol.
8.4.6.2
Pull-Up Resistor
The circuit board designer is required to place external pull-up resistors (10 k recommended) on the SPI_DO / GPIO5 / SDA / SPI_SPD_SEL and SPI_CLK / GPIO4 / SCL lines (per SMBus 1.0 Specification and EEPROM manufacturer guidelines) to VDD33 in order to assure proper operation.
8.4.7
In-Circuit EEPROM Programming
The EEPROM can be programmed via automatic test equipment (ATE). Pulling nRESET low tri-states the device's EEPROM interface and allows an external source to program the EEPROM.
8.5
Default Configuration Option
The SMSC device can be configured via its internal default configuration. Please see Section 8.3.2, "EEPROM Data Descriptor" for specific details on how to enable default configuration. Please refer to Table 8.1 for the internal default values that are loaded when this option is selected.
8.6
Reset
There are three different resets that the device experiences. One is a hardware reset from the internal power-on reset (POR) circuit, another reset is via the nRESET pin, and the third is a USB bus reset.
8.6.1
Internal POR Hardware Reset
All reset timing parameters are guaranteed by design.
8.6.2
External Hardware nRESET
A valid hardware reset is defined as assertion of nRESET for a minimum of 1 s after all power supplies are within operating range. While reset is asserted, the device (and its associated external circuitry) consumes less than 500 A of current. Assertion of nRESET (external pin) causes the following: 1. All downstream ports are disabled and PRTCTL power to downstream devices is removed. 2. The PHYs are disabled and the differential pairs will be in a high-impedance state. 3. All transactions immediately terminate; no states are saved. 4. All internal registers return to the default state (in most cases, 00h). 5. The external crystal oscillator is halted. 6. The PLL is halted.
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8.6.2.1
nRESET for EEPROM Configuration
Hardware reset asserted Device Recovery/ Stabilization 8051 Sets Configuration Registers Attach USB Upstream Start completion request response
USB Reset recovery
Idle
t4 t1
nRESET
t2
t3
t5
t6
t7
VSS
Figure 8.1 nRESET Timing for EEPROM Mode Table 8.7 nRESET Timing for EEPROM Mode NAME t1 t2 t3 t4 t5 t6 t7 DESCRIPTION nRESET asserted Device recovery/stabilization 8051 programs device configuration USB attach (See Note) Host acknowledges attach and signals USB reset USB idle Completion time for requests (with or without data stage) 100 Undefined 5 20 MIN 1 500 50 100 TYP MAX UNITS
sec sec
msec msec msec msec msec
Note: All power supplies must have reached the operating levels mandated in Chapter 10, DC Parameters, prior to (or coincident with) the assertion of nRESET.
8.6.3
USB Bus Reset
In response to the upstream port signaling a reset to the device, the device does the following: Note: The device does not propagate the upstream USB reset to downstream devices. 1. Sets default address to `0'. 2. Sets configuration to: Unconfigured. 3. Negates PRTCTL[3:2] to all downstream ports. 4. Clears all TT buffers. 5. Moves device from suspended to active (if suspended). 6. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the reset sequence. The host then configures the device and the device's downstream port devices in accordance with the USB 2.0 Specification.
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Chapter 9 AC Specifications
9.1 Oscillator/Crystal
Parallel Resonant, Fundamental Mode, 24 MHz 350 ppm.
Figure 9.1 Typical Crystal Circuit Table 9.1 Crystal Circuit Legend SYMBOL C0 CL CB CS CXTAL C1 C2 DESCRIPTION Crystal shunt capacitance Crystal load capacitance Total board or trace capacitance Stray capacitance XTAL pin input capacitance Load capacitors installed on OEM board IN ACCORDANCE WITH Crystal manufacturer's specification (See Note 9.1) OEM board design SMSC IC and OEM board design SMSC IC Calculated values based on Figure 9.2, "Capacitance Formulas" (See Note 9.2)
C1 = 2 x (CL - C0) - CS1 C2 = 2 x (CL - C0) - CS2
Figure 9.2 Capacitance Formulas Note 9.1 C0 is usually included (subtracted by the crystal manufacturer) in the specification for CL and should be set to `0' for use in the calculation of the capacitance formulas in Figure 9.2, "Capacitance Formulas". However, the OEM PCB itself may present a parasitic capacitance between XTAL1 and XTAL2. For an accurate calculation of C1 and C2, take the parasitic capacitance between traces XTAL1 and XTAL2 into account. Each of these capacitance values is typically approximately 18 pF.
Note 9.2
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9.2
Ceramic Resonator
24 MHz 350 ppm
Figure 9.3 Ceramic Resonator Usage with SMSC IC
9.3
External Clock
50% Duty cycle 10%, 24 MHz 350 ppm, Jitter < 100 ps rms. The external clock is recommended to conform to the signaling level designated in the JESD76-2 specification on 1.8 V CMOS Logic. XTAL2 should be treated as a no connect.
9.3.1
I2C EEPROM
Frequency is fixed at 58.6 kHz 20%
9.3.2
USB 2.0
The SMSC device conforms to all voltage, power, and timing characteristics and specifications as set forth in the USB 2.0 Specification. Please refer to the USB 2.0 Specification for more information.
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Chapter 10 DC Parameters
10.1 Maximum Guaranteed Ratings
SYMBOL TSTOR MIN -55 150 MAX UNITS C C VDD33 -0.5 -0.5 4.0 (3.3 V supply voltage + 2) 6 V V Please refer to JEDEC specification J-STD-020D. COMMENTS
PARAMETER Storage Temperature Lead Temperature 3.3 V supply voltage Voltage on USB+ and USB- pins Voltage on GPIO10
-0.5
VDD33 + 0.3
V
When internal power FET operation of these pins are enabled, these pins may be simultaneously shorted to ground or any voltage up to 3.63 V indefinitely, without damage to the device as long as VDD33 is less than 3.63 V and TA is less than 70oC.
Voltage on any signal pin Voltage on XTAL1 Voltage on XTAL2
-0.5 -0.5 -0.5
VDD33 + 0.3 3.6 2.0
V V V
Note: Stresses above the specified parameters may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at any condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies the absolute maximum ratings must not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, a clamp circuit should be used.
Voltage VDD33
tRT
3.3 V 100%
90%
VSS
10%
t10%
t90%
Time
Figure 10.1 Supply Rise Time Model
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10.2
Operating Conditions
SYMBOL TA 0 MIN 70 MAX UNITS C COMMENTS Ambient temperature in still air.
PARAMETER Commercial USB4640 Operating Temperature Industrial USB4640i Operating Temperature 3.3 V supply voltage
TA
-40
85
C
Ambient temperature in still air.
VDD33
3.0
3.6
V
A 3.3 V regulator with an output tolerance of 1% must be used if the output of the internal power FET's must support a 5% tolerance. (Figure 10.1) If any 3.3 V supply voltage drops below 3.0 V, then the MAX becomes: (3.3 V supply voltage) + 0.5 5.5
3.3 V supply rise time Voltage on USB+ and USB- pins
tRT
0 -0.3
400 5.5
s
V
Voltage on any signal pin Voltage on XTAL1 Voltage on XTAL2
-0.3 -0.3 -0.3
VDD33 2.0 2.0
V V V
10.3
DC Electrical Characteristics
PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS
I, IPU, IPD Type Input Buffer Low Input Level High Input Level Pull Down Pull Up IS Type Input Buffer Low Input Level High Input Level Hysteresis VILI VIHI VHYSI 2.0 420 0.8 V V mV TTL Levels VILI VIHI PD PU 2.0 72 58 0.8 V V
A A
TTL Levels
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PARAMETER ICLK Input Buffer Low Input Level High Input Level Input Leakage Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage I/O6, I/OD6PU Type Buffers Low Output Level
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VILCK VIHCK IIL 1.4 -10
0.5
V V
+10
A
VIN = 0 to VDD33
IIL IIH
-10 -10
+10 +10
A A
VIN = 0 VIN = VDD33
VOL High Output Level VOH Output Leakage IOL Pull Down PD Pull Up PU O8, O8PD, 08PU, I/O8, I/O8PD, and I/O8PU Type Buffers Low Output Level VOL 58 72 -10 VDD33 - 0.4
0.4
V
IOL = 6 mA @ VDD33 = 3.3 V
V
IOH = -6 mA @ VDD33 = 3.3 V
+10
A
A A
VIN = 0 to VDD33 (Note 10.1)
0.4
V
IOL = 8 mA @ VDD33 = 3.3 V
High Output Level
VOH
VDD33 - 0.4
V
IOH = -8 mA @ VDD33 = 3.3 V
Output Leakage
IOL PD PU
-10
+10
A
A A
VIN = 0 to VDD33 (Note 10.1)
Pull Down Pull Up
72 58
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PARAMETER O12, I/O12, and I/O12PD Type Buffers Low Output Level
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL
0.4
V
IOL = 12 mA @ VDD33 = 3.3 V
High Output Level
VOH
VDD33 - 0.4
V
IOH = -12 mA @ VDD33 = 3.3 V
Output Leakage
IOL PD PU
-10
+10
A
A A
VIN = 0 to VDD33 (Note 10.1)
Pull Down Pull Up IO-U I-R I/O200 Integrated Power FET for GPIO10 High Output Current Low Output Current (Note 10.4) On Resistance (Note 10.4) Output Voltage Rise Time Integrated Power FET Set to 100 mA Output Current (Note 10.4) Short Circuit Current Limit On Resistance (Note 10.4) Output Voltage Rise Time Integrated Power FET Set to 200 mA Output Current (Note 10.4) Short Circuit Current Limit On Resistance (Note 10.4) Output Voltage Rise Time
72 58
Note 10.2 Note 10.3
IOUT IOUT RDSON tDSON
200 100 2.1 800
mA mA
s
VdropFET = 0.46 V VdropFET = 0.23 V IFET = 70 mA CLOAD = 10 F
IOUT ISC RDSON tDSON
100 140 2.1 800
mA mA
s
VdropFET = 0.22 V VoutFET = 0 V IFET = 70 mA CLOAD = 10 F
IOUT ISC RDSON tDSON
200 181 2.1 800
mA mA
s
VdropFET = 0.46 V VoutFET = 0 V IFET = 70 mA CLOAD = 10 F
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SMSC USB4640/USB4640i
High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
PARAMETER Supply Current Unconfigured Hi-Speed Host USB4640 USB4640i Full Speed Host USB4640 USB4640i Supply Current Configured Hi-Speed Host, 1 downstream port USB4640 USB4640i Supply Current Configured Hi-Speed Host, each additional downstream port USB4640 USB4640i Supply Current Configured Full-Speed Host, 1 downstream port USB4640 USB4640i Supply Current Configured Full-Speed Host, each additional downstream port USB4640 USB4640i HSIC_DAT, HSIC_STROBE Driver Impedance Supply Current Active Supply Current Suspend Supply Current Reset
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS Note 10.6
ICCINTHS ICCINTHS
TBD TBD
TBD TBD
mA mA
ICCINITFS ICCINITFS
TBD TBD
TBD TBD
mA mA Note 10.6
IHCH1 IHCH1
TBD TBD
TBD TBD
mA mA
TBD TBD
TBD TBD
mA mA
IFCC1 IFCC1
TBD TBD
TBD TBD
mA mA
TBD TBD ID ICC ICSBY IRST TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD
mA mA
mA A A
Note 10.5 Note 10.6
Note 10.1 Output leakage is measured with the current pins in high impedance. Note 10.2 See the USB 2.0 Specification, Chapter 7, for USB DC electrical characteristics Note 10.3 RBIAS is a 3.3 V tolerant analog pin. Note 10.4 Output current range is controlled by program software. The software disables the FET during short circuit condition. Note 10.5 Please refer to the USB 2.0 supplement "High-Speed Inter-Chip USB Electrical Specification Revision 1.0 as of September 23, 2007" which can be obtained from http://www.usb.org/developers/docs/docs. Note 10.6 Typical and maximum values were characterized using the following temperature ranges: The USB4640 supports the commercial temperature range of 0C to +70C The USB4640i supports the industrial temperature range of -40C to +85C
SMSC USB4640/USB4640i
DATASHEET
59
Revision 1.0 (06-09-09)
High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
10.4
Capacitance
TA = 25C; fc = 1 MHz; VDD33= 3.3 V Table 10.1 Pin Capacitance LIMITS PARAMETER SYMBOL CXTAL MIN TYP MAX 2 UNIT pF TEST CONDITION All pins (except USB pins and pins under test) are tied to AC ground.
Clock Input Capacitance
Input Capacitance Output Capacitance
CIN COUT
10 20
pF pF
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SMSC USB4640/USB4640i
High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
Chapter 11 GPIO Usage
Table 11.1 USB4640/USB4640i GPIO Usage NAME GPIO1 GPIO2 GPIO4 GPIO5 GPIO6 GPIO10 GPIO12 GPIO14 GPIO15 ACTIVE LEVEL H H H H L L L L L SYMBOL LED / TxD RxD SCL SDA SD_WP CRD_PWR_CTRL MS_nCD xD_nCD SD_nCD DESCRIPTION AND NOTE LED indicator / Serial port transmit line Serial port receive line Serial EEPROM clock Serial EEPROM data Secure Digital card write protect assertion Card power control Memory Stick card detect xD-Picture card detect Secure Digital card detect
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DATASHEET
61
Revision 1.0 (06-09-09)
High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
Chapter 12 Package Specifications
Figure 12.1 USB4640/USB4640i 48-Pin QFN
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SMSC USB4640/USB4640i
High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
12.1
Tape and Reel Specifications
Figure 12.2 48-Pin Package Tape Specifications
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DATASHEET
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Revision 1.0 (06-09-09)
High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller Datasheet
Figure 12.3 48-Pin Package Reel Specifications
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SMSC USB4640/USB4640i

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